1. Technical Field of the Invention
The present invention relates to DFSE decoders, and more particularly, to the improvement of coding gain performance in Gigibit Phy Viterbi Decoders.
2. Description of the Related Art
Gibabit Ethernet over copper medium is a rapidly evolving technology enabling one gigabit per second full duplex communication over existing category 5 twisted pair cable plants. 1 Gb/s communication throughput is achieved with four pairs of twisted pair cables and eight transceivers 40 (four at each end) operating at 250 Mb/s as depicted in FIG. 1. Modulation between the transmitting and receiving ends use baseband 5-level pulse amplitude modulation (PAM5) combined with trellis coding and partial response shaping as the basis for the transmission scheme. Eight bits of data are encoded to nine bits and these nine bits are encoded to four PAM5 signals. The information for any particular bit becomes spread over all channels.
FIG. 2 illustrates a block diagram of a 100 Base-T transceiver 45 used within the system in FIG. 1. The Gigabit Medium Independent Interface (GMII) 50 receives data in a byte-wide format at a rate of 125 MHz and passes the data on to a Physical Coding Sublayer (PCS) 55 which performs scrambling, coding and a variety of control functions. Except for the GMII 50 and PCS 55 blocks, FIG. 2 illustrates only one out of the four channels of the transceiver 45. The other three channels of the transceiver 45 have a similar block diagram. Within the PCS 55, eight bits of data are encoded to nine bits and these nine bits are encoded to four PAM5 signals. The corresponding symbol for each channel goes through a 0.75+0.25 z−1 shaping at pulse shaper 60 followed by conversion at a 125 MHz D/A converter 65. Low-pass filtering and line driver/hybrid circuitry 70 further process the signal before transmission on the twisted pair wire.
On the receiver path, a received analog signal is preconditioned by the hybrid circuitry 70, and next goes through a 125 MHz A/D converter 75 sampled by a clock signal provided by the decision-directed timing recovery circuit 80. The output of the A/D converter 75 is filtered by a Feed Forward Equalizer (FFE) 85 which is an LMS-type adaptive filter performing channel equalization and precursor Inter Symbol Interference (ISI) cancellation. The symbols sent by the other three local transmitters cause impairments in the received signal for each channel through a near end crosstalk mechanism between the pairs. Since each receiver has access to data from the other three transmitters that cause the interference, it is possible to nearly cancel the effects of the interference. Cancellation is accomplished with three adaptive NEXT canceling filters 90. The output of the NEXT canceling filters 90 are added to the FFE 85 output to cancel the interference. Similarly, because of the bidirectional nature of the channel, an echo impairment is caused by each transmitter on its own receiver signal. This impairment is also nearly canceled using an echo canceled 95, another adaptive filter, whose output is also directly added to the FFE 85 output.
The outputs of the FFE 85, echo canceled 95 and the three NEXT chancellors 90 are combined with the output of the adaptive feedback filter and input to the Decision Feedback Sequence Estimation (DFSE) Viterbi decoder 100 as partially equalized channel values to generate a soft decision. Inside the DFSE equalization is completed on each of four channels resulting in soft decisions which are further processed by the decoder to obtain the most likely eight bit value for the current sample. The operation of the DFSE Viterbi decoder 100 and the algorithm executed thereby more fully described in “Design Considerations for Gigabit Ethernet 100 Base-T Twisted Pair Transceivers”, Hatamian et al. IEEE 1998 Custom Integrated Circuits Conference, pp. 335-342 and “A 1-Gb/s Joint Equalizer and Trellis Decoder for 100 Base-T Gigabit Ethernet”, Haratsch and Azadet, IEEE Journal of Solid State Circuits, Vol. 36, No. 3, March 2001, pp. 374-384 which are incorporated herein by reference. The DFSE Viterbi decoder 100 is also referred to as a 8 state Decision Feedback Equalizer (DFE) Viterbi decoder.
In practice, DFSE decoder 100 suffers from an error propagation effect. Error propagation describes the process of incorrect decisions within a Viterbi traceback memory being propagated through DFE filters and causing increased noise and errors at the input of the Viterbi decoder 100. As a result, the coding gain of such a system is in practice less than five decibels for a particular 100 meter channel and degrades further as the channel lengthens and the magnitude of the DFE coefficient increases. Another challenge within 8-DFE Viterbi decoders is the critical path of the circuitry required for a hardware implementation limits the addition of new hardware to improve gain performance. Thus, there is a need to increase coding gain performance and provide performance and immunity against large coefficient values within DFE filters while not adding additional circuitry within the already tightly constrained critical path of a DFSE Decoder.